Sr Principal Software Engineer, Innovus — Physical Synthesis & Optimization

About this role

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Why Cadence? — Design for AI. AI for Design.

Cadence sits at the intersection of semiconductor innovation and high-performance computing. Through Design for AI, our EDA technologies enable the advanced silicon platforms powering modern AI infrastructure. Through AI for Design, we integrate machine learning, data-driven optimization, and intelligent automation into our industry-leading implementation flows to transform how chips are designed.

As part of the Innovus R&D team, you will build high-performance software engines and algorithms behind next-generation physical synthesis, helping push the boundaries of performance, power, area (PPA), timing closure, and design productivity at scale.

Role Overview

We are looking for a Senior / Staff Software Engineer to contribute to the design and development of next-generation physical synthesis and optimization engines within Innovus.

In this hands-on engineering role, you will solve challenging computational problems at the intersection of advanced graph/spatial algorithms, high-performance C++, parallel and distributed computing, and large-scale numerical optimization. Your work will operate at semiconductor scale—where algorithmic efficiency, memory footprint, and multi-core scalability directly impact the ability to design billions of transistors on advanced process nodes.

Key Responsibilities

• Core Engine & Algorithm Development
• Design, implement, unit-test, and optimize high-performance C++ engines for physical synthesis, placement, and timing-driven optimization.
• Develop advanced graph algorithms, spatial data structures, and continuous/combinatorial optimization techniques for massive-scale physical design workloads.
• Identify and eliminate CPU bottlenecks, memory footprint overhead, and algorithmic scaling limits in production C++ codebases.
• Translate research concepts and mathematical formulations into robust, maintainable, production-quality software.
• Parallel & Distributed Computing
• Implement multi-threaded and distributed algorithms for computationally intensive implementation engines.
• Scale physical design workloads across multi-core systems and compute clusters while minimizing synchronization overhead and memory bandwidth constraints.
• Apply modern profiling and benchmarking tools to maximize CPU utilization, cache efficiency, and execution throughput.
• Physical Design Optimization & R&D
• Develop physical design optimization modules addressing timing, power, performance, area (PPA), and congestion.
• Work directly with large-scale layout and netlist data to build practical, highly scalable optimization strategies.
• Collaborate with R&D colleagues to integrate data-driven and AI-assisted optimization heuristics into core synthesis flows.

Qualifications

• Required
• Education: Master’s or Ph.D. in Computer Science, Electrical Engineering, Computer Engineering, or a related quantitative field (or equivalent hands-on industry experience).
• C++ Expertise: Strong hands-on experience developing high-performance, production-quality C++ (C++17/20) in Linux environments.
• Core Fundamentals: Solid foundation in data structures, graph algorithms, computational geometry, memory management, and software architecture.
• Concurrent Programming: Practical experience with multithreaded or concurrent programming and low-level performance profiling.
• Problem Solving: Proven ability to analyze, debug, and optimize complex algorithmic bottlenecks in large-scale software systems.
• Preferred
• EDA / Physical Design: Prior experience developing EDA tools, with specific knowledge in physical synthesis, global/detail placement, static timing analysis (STA), routing, or timing closure.
• AI & Machine Learning: Exposure to applying machine learning, deep learning, reinforcement learning, or data-driven heuristics to software optimization problems.
• Scripting & Tooling: Proficiency with Python, Tcl, or shell scripting for benchmarking and workflow automation.
• HPC & Acceleration: Experience with SIMD vectorization, GPU/CUDA acceleration, or large-scale distributed compute frameworks.
• The Opportunity

This role is ideal for a hands-on developer who loves tackling hard algorithmic and systems-level problems at massive scale. Whether your background is rooted deeply in EDA or high-performance systems C++, you will directly write the foundational software engines that power the next generation of global silicon innovation.

• Build the engines. Scale the algorithms. Shape the future of chip implementation.

The annual salary range for California is $161,000 to $299,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

• We’re doing work that matters. Help us solve what others can’t.